System-Level Synthesis and VerificationPublic Deposited
As device sizes decrease, more functionality can be placed in an integrated circuit. Therefore, the design complexity of these circuits increases. To deal with complexity, designers move to higher abstraction levels. Currently, the highest abstraction level is the system-level. In our work we investigate the synthesis and verification problem at the system-level. We examine ways to increase the energy efficiency of specific system-level designs. Moreover, we propose an algorithm to retime a system-level description, so that its performance becomes optimal. Retiming is a powerful synthesis operation that can be used to change the schedule of a design. We investigate the optimization power of synthesis operations, like retiming, and propose a sequence of synthesis operations that is complete for the transformation of sequential circuits. The verification problem is hard. Checking equivalence between two designs or checking whether a design satisfies a given assertion is proven to have high computational complexity in the general case. We describe ways to simplify the verification problem. First, we show that the verification problem can be simplified by considering it during synthesis without restricting the optimization power of the synthesis operations. Then we show how abstraction can enable the use of efficient automated verification tools.