Circuit-level Dynamic Timing Slack (DTS) has emerged as a compelling opportunity for eliminating inefficiency in modern low-power systems. This slack arises when all the signals have propagated through logic paths well in advance of the clock signal. When it is properly identified, the system can exploit this unused cycle time for energy savings. This work introduces a novel cross-layer fashion to exploit the DTS for energy efficiency. Based on the connections between high-level instruction sequences and low-level circuit transitions, the DTS can either be identified in a speculative or non-speculative manner. With Time Speculative (TS) systems, timing error models can be dynamically built through the use of supervised learning. For non-speculative systems, a Footprint delay model is proposed to provide the tighter upper bound of circuit-level delay based on micro-architectural state transitions. These cross-layer models bridge the ISA-level instruction patterns with circuit-level timing characteristics. Enhanced by hardware features including fined-grained voltage management and fast clock phase adjustment, energy consumption of the pipeline may be dramatically reduced at run-time, with the guidance of compiler and code transformations that target at this co-designed architecture. In this work, we propose cross-layer techniques to exploit circuit-level timing slack and demonstrate the significant opportunities to improve energy efficiency.

Creator

• Fan, Yuanbo

DOI

• https://doi.org/10.21985/n2-8jhy-9x70

Subject

• Computer engineering

Language

• en

Alternate Identifier

• etdadmin_upload_624514
• http://dissertations.umi.com/northwestern:14433

Keyword

• code transformation
• Dynamic timing slack
• timing error model
• timing speculation
• energy efficiency
• low power

Date created

• 2018-01-01

Resource type

• Dissertation

Rights statement

• In Copyright