High Performance Caches and Interconnects for Many-Core and 3D Integrated CircuitsPublic Deposited
Integrated circuits have been continuously scaled to increase speed and integration density as a means to improve the performance or pack more functionality. However, an extremely enormous amount of effort is needed to further scale the dimensions in deep submicron technologies. As technology scaling is slowing down and design complexity is currently extremely high, the capacity of increasing performance through scaling or adding more complexity is limited. The ITRS have predicted that the performance is likely to saturate unless a paradigm shift from present integrated circuits architecture is introduced. Recently, two major paradigm shifts evolved and proved to have tremendous potential; many-core microprocessors and 3D integrated circuits. In many-core microprocessors, the concept of parallelism in computation, which was used in supercomputers, proves to be a very attractive solution to boost the performance without increasing the speed or multiplying the complexity. In 3D integrated circuits, the number of long interconnects as well as the overall length of interconnects are significantly reduced, which readily translates into reduction in propagation delays, increase in speed and performance, and reduction in power dissipation. This work focuses on some of the important problems related to the design of many-core microprocessors and 3D integrated circuits, specifically, problems related to cache analysis and design, as well as, interconnects design and modeling. Cache is a very important block in modern microprocessors. The size of cache nearly doubles every generation. The efficient design of caches is an extremely important factor in the performance of future microprocessors. Interconnects are another extremely important factor in the performance. Integrated circuits performance is currently dominated by the interconnects, which represents a major bottleneck in increasing performance. An accurate technique for SRAM dynamic stability estimation is proposed and applied to several important case studies. It enables evaluation of stability in real operation conditions and for different dynamic circuit techniques. The effects of power supply AC noise on SRAM dynamic stability are studied. Measurements of a test chip in 65nm technology are in agreement with the presented theory and simulations. Several dynamic circuit techniques for cache supply voltage reduction are studied. Using a 32kB level-1 data cache in 45nm technology, performance improvements and area overhead are evaluated for all techniques. An area-efficient high-speed low-power wave-pipelined global interconnect link design is proposed. Based on a 10mm global link design in 90nm technology, results indicate enormous improvements in all the aspects of performance. Analytical models for propagation delay and rise time of TSVs in 3D integrated circuits in terms of the physical dimensions are presented. They provide good accuracy and fidelity in addition to simplicity, which makes them very useful in the analysis of 3D integrated circuits. To simplify the initial design of power grids, reduced circuit models and simple analytical models for the IR drop and the frequency response are presented. In addition, optimum sizing of power grid interconnect lines for minimum IR drop is derived, which provides good reduction in IR drop with equal metal resources.
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