An efficient unified incremental high-level and physical-level synthesis algorithm was presented in Chapter 2, which enable the tight integration between high-level and physical-level design. Chapter 3 presented a temperature-aware high-level synthesis algorithm built upon the framework of Chapter 2. Temperature variations and hot spots account for reliability issue and require...
With aggressive scaling down of feature sizes in VLSI fabrication, process variations, crosstalk and buffering have become critical issues to achieve timing closure in VLSI designs. Timing analysis and optimization techniques need to consider each of them and also their interactions. There are many statistical timing analysis researches to handle...