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Timing Analysis and Optimization Techniques for VLSI Circuits

Description:

With aggressive scaling down of feature sizes in VLSI fabrication, process variations, crosstalk and buffering have become critical issues to achieve timing closure in VLSI designs. Timing analysis and optimization techniques need to consider each of them and also their interactions. There are many statistical timing analysis researches to handle...

Keyword:

Crosstalk, Timing analysis, VLSI, Process variations, Optimization, and Buffer

Subject:

Electrical and Computer Engineering

Creator:

Rui Ming Chen

Owner:

Scholarly Digital Publishing

Date Uploaded:

08/28/2018

Date Modified:

08/28/2018

Date Created:

2007-12-14

Resource Type:

Dissertation