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Exploiting Circuit-Level Timing Slack for Energy Efficiency

Description:

Circuit-level Dynamic Timing Slack (DTS) has emerged as a compelling opportunity for eliminating inefficiency in modern low-power systems. This slack arises when all the signals have propagated through logic paths well in advance of the clock signal. When it is properly identified, the system can exploit this unused cycle time...

Keyword:

code transformation, Dynamic timing slack, timing error model, timing speculation, energy efficiency, and low power

Subject:

Computer engineering

Creator:

Fan, Yuanbo

Owner:

Scholarly Digital Publishing

Language:

en

Date Uploaded:

02/12/2020

Date Created:

2018-01-01

Resource Type:

Dissertation

Alternate Identifier:

etdadmin_upload_624514 and http://dissertations.umi.com/northwestern:14433