Low-Power Mixed-Signal Time-Domain Hardware Accelerator Design for Edge Computing and Machine Learning

Chen, Zhengyu

doi:https://doi.org/10.21985/n2-xjb0-af22

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Low-Power Mixed-Signal Time-Domain Hardware Accelerator Design for Edge Computing and Machine Learning

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While the entire silicon industry has been blooming under Moore’s Law for decades, conventional digital implementation is approaching the “stall” of Moore’s Law due to many physical design limitations. Technology innovation now is going to take a different direction. Given the increasing demand for emerging applications' computational capacity, it is urgent to find alternative computing methods that can bring efficiency beyond conventional digital approach. To improve the computing efficiency, multiple alternative solutions have been proposed, e.g. approximate computing, parallel computing, quantum computing, time-domain computing, etc. Among them, mixed-signal time-domain computing (MSTC) has drawn significant attention recently due to its high energy efficiency and low area cost. As the nature of mixed-signal design, MSTC combines the advantages of both digital and analog computing methods. On one hand, circuit-wise, MSTC utilizes digital components to encode/decode and processes information in time domain, which brings the benefit of technology scalability and compatibility of the current digital design flow. On the other hand, from the signal processing aspect, MSTC is similar to analog computing as the information can be more densely encoded in a single signal, e.g. a time pulse, leading to benefits similar to the analog-based processing. Such benefits include the high efficiency in energy consumption and a desirable error resiliency/scalability where most-significant-bit is the least likely to show errors.In this thesis, the innovative MSTC circuit, architecture, and algorithm design methodology are introduced to accelerate emerging applications, e.g. image processing and machine learning. To provide a concrete circuit design foundation, the variation-aware MSTC circuit design methodology is introduced. The basic arithmetic cells and other complex operation modules including time flip-flop, time-domain accumulator, and time-domain multiplier, are implemented in time domain. To demonstrate the energy and area efficiency in conducting non-linear operations, a MSTC-accelerated image processing engine is presented with over 40% area and energy improvement compared to the digital counterparts. To improve the throughput in MSTC, the first time-domain pipeline architecture for dynamic time warping (DTW) algorithm is proposed, which is enabled by the special time flip-flop design. The proposed pipeline operation leads to an order of magnitude improvement in throughput and a scalable processing capability for time series classification tasks. Moreover, to demonstrate the efficiency in conducting machine learning workloads, a MSTC-based accelerator for deep neural network (DNN) applications, i.e. generative adversarial network (GAN), is developed. The proposed GAN accelerator is the first mixed-signal circuit implementation with efficient multi-bit multiplication for on-chip DNN inference and training. Different from prior time-based implementations which need successive conversion between time and digital domain when realizing MAC operation, this work computes the entire MAC operation in time domain, rendering the highest throughput of 18~5400× with similar efficiency. To explore the potential in carrying the emerging Compute-In-Memory (CIM) task, an energy efficient time-domain CIM processor is proposed. A single-phase MAC operation is realized to remove throughput overhead of prior multi-phase operation and digital accumulation. The power bottleneck of ADC/SA is mitigated by implementing a computation-adaptive ADC skipping operation and special analog sparsity scheme, leading to additional 2~3× reduction of CIM macro power. Finally, to deliver the missing element of design automation for time-based design and to make it compatible with the existing digital design flow, a systematic design automation flow for MSTC is presented. More specifically, a digital compatible synthesis and backend flow is developed with novel variation-aware RTL mapping and ACG-based placement algorithms to enable the automation of MSTC design. Compared to the existing analog placement methods and commercial EDA tools, the proposed design automation scheme shows significant improvement in the signal matching performance.

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