System-Level Optimizations for High Performance DSM Circuits

Jia Wang

doi:https://doi.org/10.21985/N2MH9P

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System-Level Optimizations for High Performance DSM Circuits

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Process scaling has enabled the production of integrated circuits with millions of transistors. System-on-a-Chip becomes feasible as more functionalities can be packed into a single chip. As the human brain power is limited, the design process of such sophisticated systems should be automated in order to meet the stringent design specifications and short time-to-market. On one hand, ever-increasing system sizes require scalable algorithms for efficient system design space exploration. On the other hand, shrinking VLSI feature sizes require previous ignored physical effects to be considered for the reliability and manufacturability of the system. In this dissertation, we will present a few essential advances in design automation of high performance DSM circuits for the above challenges. We investigate floorplanning techniques in order to address the methodology shift from logic centric to interconnect centric. We propose the processing rate as an unified performance measure and develop a floorplanning approach to optimize it directly through efficient minimum cycle ratio algorithms. Then, we present two graph-based floorplan approaches -- one of them models the adjacency relations between the non-overlapping rectangular blocks, and the other models the non-overlapping constraints between the blocks, while the sizes of both graphs are linear in terms of the number of the blocks. Moreover, we investigate sequential system optimization techniques for system optimizations under performance bounds. We propose to combine sizing and clock skew optimization in a convex-programming-based framework and design an algorithm to solve the problem based on the method of feasible directions and min-cost network flow. We then present an optimal minimum area retiming algorithm that incrementally relocates flip-flops in a sequential circuit without changing its functionality subject to a clock period bound. Compared to the conventional algorithms that solve the same problem, our algorithm only requires linear storage and is practically much more efficient. Further more, we investigate design for manufacturability techniques to consider issues in chip fabrication at the design time. We propose to perform risk-aversion min-period retiming in order to overcome process variations through retiming and present a heuristic incremental retiming algorithm. We study the antenna effect during fabrication process that damages gates and design an optimal algorithm in routing stage to insert jumpers under a bound of antenna ratio such that the damages of antenna effects will be limited.

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